The present invention relates to a control system for the peripheral component interconnect bus, more commonly known as the PCI bus.
The PCI bus is used to connect peripheral devices to a host processor in a computing device such as a personal computer. One feature of the PCI bus is that it requires extensive initialization by software each time the computer is switched on or reset. In a typical personal computer system, the peripheral devices are non-intelligent, and the entire initialization process is carried out by the host processor itself, acting as the PCI bus master. Subsequent communication on the PCI bus is also controlled centrally by the host processor.
A problem with this centralized initialization and control scheme is that since the host processor must access all of the devices connected to the bus, it needs to have drivers for all of these devices. Furthermore, the host processor must sometimes copy data from one device to another even if the data are irrelevant to the host processor itself.
Use of, the PCI bus is not limited to personal computers; it can be used advantageously for interconnecting both embedded and peripheral components in many types of computing systems and other systems, some of which may have a plurality of intelligent devices residing on the same PCI bus. Various further problems arise in these systems, however, including the problem of how to establish communication among a plurality of intelligent devices, how to assign responsibility for managing non-intelligent devices, and how to carry out the initialization process in an orderly manner. The present invention addresses these problems.
One object of the present invention is to enable services provided by non-intelligent devices to be initialized and managed by intelligent devices;
Another object is to simplify the identification of intelligent and non-intelligent devices;
Another object is to simplify communication with intelligent devices during low-level initialization;
Another object is to simplify communication among intelligent devices during higher-level initialization;
Another object is to facilitate the control of higher-level initialization;
Another object is to facilitate the transmission of data divided into a plurality of blocks;
Another object is to facilitate the processing of transmitted data.
The invented PCI bus control system operates in a PCI bus environment having a PCI bus master and a plurality of connected devices, including both intelligent devices which can initiate PCI bus transactions, and non-intelligent devices which cannot do so. Each non-intelligent device is owned and managed by an intelligent device, which relays access requests from other devices to the non-intelligent device. The services provided by non-intelligent devices can thus be initialized and managed by intelligent devices.
Intelligent and non-intelligent devices are preferably distinguished by a predetermined number of leading bits in a configuration register, provided in each device, that is read during, initialization. Intelligent and non-intelligent devices can thus be easily distinguished.
In the memory address space of the PCI bus system, the area allocated to each intelligent device preferably begins with a predefined communication area, which becomes available for sending commands and requests as soon as the memory address space has been mapped. This simplifies communication between the PCI bus master and the intelligent devices during low-level initialization.
Each intelligent device preferably also has a device control table including device profiles of the device functions of other devices, and has a PCI interrupt request register for receiving interrupt requests from other intelligent devices. For any two intelligent device functions X and Y, the device profile of function Y in the device control table of function X preferably includes a pointer to the PCI interrupt request register of function Y, and a pointer to a mailbox area in the device profile of function X in the device control table of function Y. This arrangement facilitates communication during higher-level initialization. The device control tables are preferably created and distributed by the PCI bus master. The PCI interrupt request register is preferably bit-mapped.
The PCI bus master itself may coordinate the higher-level initialization process, or it may select another device to do so, in which case the PCI bus master operates as a temporary initialization master during the selection of the other device. The selected device becomes a xe2x80x98device master.xe2x80x99 Allowing other devices to become the device master simplifies the control of higher-level initialization.
When a series of data blocks are transmitted from a transmitting device to a receiving device on the PCI bus, by being copied by the receiving device, the data blocks preferably have headers giving the data address and size, each header being linked by a pointer to the header of the next data block in the series. The headers may also indicate whether or not the data blocks must be copied to contiguous areas. These arrangements facilitate the rapid copying of data, and the copying of data from diverse areas into a single continuous area.
The PCI bus control system may have a hierarchical processing structure with an upper layer, an intermediate layer, and a lower layer. When passing data from the upper layer to the lower layer, the intermediate layer attaches its own header to the data. The attached header is preferably padded to align the data on a predetermined type of boundary. This facilitates the processing of the data by a device receiving the data.